Hardware
OpenEVCharger v1 targets STM32F2-compatible Cortex-M3 EVSE controllers. The core (FreeRTOS task layout, J1772 state machine, OCPP/TLV protocol, OTA, RTC bridge, persistence) is board-independent. Adding a board means producing three artefacts: the GPIO pin map, the linker script, and the CMake target config.
Bench-validated
| Board | MCU | Status | Notes |
|---|---|---|---|
| Rippleon ROC001 | GD32F205VG | Bench-validated through M7, GFCI live, OTA, RTC bridge | Single-phase 6–48 A, BL0939 metering, FC41D Wi-Fi/BLE module on UART4. Pin map fully reverse-engineered from stock V1.0.066. OEM is NewEnergy CS; ROC002–010 are likely close siblings but unverified. |
Wishlist / open ports
- Nexcyber NECS-ACW family. Different OEM, different MCU (Nations N32G45x), different Wi-Fi module (Tuya WBR2 / RTL8720CF AmebaZ2), and a different cloud architecture — Nexcyber is a stock Tuya device, whereas Rippleon runs a custom OCPP/REST backend behind the FC41D. Not interchangeable with Rippleon ROC. Hardware on hand; port not started.
Porting outline
What porting actually involves, in rough order:
- MCU bring-up. Clock tree and UART logger come up.
printk()over the debug UART confirms the chip is alive at the right frequency. - Pin map. Produce
src/core/pin_map_<board>.h: relay drive + sense, CP PWM out + sense ADC, CC sense, GFCI sense, PE continuity, AC absent, NTCs, button matrix, LEDs, SPI to external NOR, UART to comms module. - HAL re-pointing. Adjust SPL include paths in CMake if the chip is a different family. Most peripheral code uses legacy F1/F2 SPL idioms.
- Linker script. Match the chip's flash + RAM size and the
.ramfuncregion for the OTA apply path. - Re-validate safety detectors with bench gear: GFCI, relay weld, over-temp, J1772 state machine. Detectors are written to spec but threshold tuning is per-board.
Full porting guide: BOARDS.md in the firmware repo.